An AND gate produces logic 1 only when:

An OR gate produces logic 0 only when:

A NOT gate is also called an:

A NAND gate is an AND gate followed by a:

A NOR gate is an OR gate followed by a:

The XOR gate output is 1 when its inputs are:

The XNOR gate output is 1 when its inputs are:

Which gate is known as a universal gate?

Which pair of gates are universal gates?

The Boolean expression for an AND operation is usually written with:

The Boolean expression for an OR operation is usually written with:

The complement of A is commonly written as:

According to the identity law, A + 0 equals:

According to the identity law, A·1 equals:

According to the null law, A + 1 equals:

According to the null law, A·0 equals:

According to the idempotent law, A + A equals:

According to the idempotent law, A·A equals:

According to the complement law, A + A' equals:

According to the complement law, A·A' equals:

The involution law states that (A')' equals:

The commutative law for OR is:

The commutative law for AND is:

The associative law for OR is:

The distributive law of AND over OR is:

De Morgan's theorem states that (AB)' equals:

De Morgan's theorem states that (A + B)' equals:

The absorption law A + AB simplifies to:

The absorption law A(A + B) simplifies to:

A buffer gate is used mainly to:

The output of a 2-input XOR gate for inputs 1 and 1 is:

The output of a 2-input XNOR gate for inputs 0 and 0 is:

The Boolean expression A + BC can be converted using distributive law to:

A truth table lists:

The number of rows in the truth table of a 3-variable function is:

A minterm is a product term that contains:

A maxterm is a sum term that contains:

The expression Y = A⊕B⊕Cin is commonly the sum output of a:

A Karnaugh map is primarily used to:

A 2-variable K-map contains:

A 3-variable K-map contains:

A 4-variable K-map contains:

Adjacent cells in a K-map differ in:

K-map adjacency follows:

In K-map grouping, valid group sizes are powers of:

Which of the following is a valid K-map group size?

The purpose of making the largest possible K-map groups is to:

A pair in a K-map eliminates:

A quad in a K-map eliminates:

An octet in a 4-variable K-map eliminates:

A group of 16 in a 4-variable K-map simplifies to:

K-map edges are considered adjacent because the map:

A don't-care condition may be used to:

The term essential prime implicant means:

Prime implicants are:

The Quine-McCluskey method is also called the:

The Quine-McCluskey method is especially useful for:

In the tabulation method, terms are first grouped by:

Two terms can be combined in Quine-McCluskey if they differ in:

The symbol '-' in Quine-McCluskey indicates:

Sum-of-products form is an OR of:

Product-of-sums form is an AND of:

A canonical SOP expression is formed from:

A canonical POS expression is formed from:

Boolean simplification aims to reduce:

The simplified expression usually produces the same:

In a K-map, overlapping groups are:

For POS minimization using a K-map, we group:

A singleton 1 in a K-map represents:

The minimum number of literals in an implicant occurs with:

K-maps are practical mainly up to about:

The main limitation of K-maps is that they become hard to use for:

A redundant group in K-map minimization is one that:

When minimizing a function, don't-care cells may be treated as:

The tabulation method gives a systematic way to find:

A combinational circuit's output depends on:

A half adder adds:

The outputs of a half adder are:

The sum output of a half adder is implemented using:

The carry output of a half adder is implemented using:

A full adder adds:

A full adder has how many inputs?

The carry-out of a full adder is 1 when:

A half subtractor provides:

A full subtractor has inputs A, B and:

An encoder converts:

A decoder converts:

A 2-to-4 decoder has:

The number of outputs of an n-to-2^n decoder is:

A priority encoder is different from a normal encoder because it:

A multiplexer selects:

A 4-to-1 multiplexer has:

A demultiplexer routes:

Which combinational block can implement Boolean functions by data selection?

A comparator is used to:

A magnitude comparator determines whether:

A code converter changes:

A BCD-to-7-segment decoder drives:

A parity generator is used for:

Even parity means the total number of 1s is:

A carry look-ahead adder is designed to:

Ripple carry adders are slower because carry:

The output of a decoder is usually:

An active-low output is asserted when it is:

A tri-state buffer can output:

High impedance state is commonly denoted by:

A bus is typically shared using:

A PLA stands for:

A ROM-based combinational design stores:

A combinational circuit has ____ memory.

Hazards in combinational logic are unwanted:

Static hazards are often reduced by adding:

A full adder can be built using:

A sequential circuit differs from a combinational circuit because it has:

The basic memory element in digital electronics is a:

An SR latch has inputs:

The forbidden condition in a NOR-based SR latch occurs when:

A gated latch is controlled by an:

A D latch eliminates the invalid SR condition by ensuring:

A flip-flop is generally:

A D flip-flop stores the value of D on the:

The characteristic equation of a D flip-flop is:

A T flip-flop toggles when T equals:

A T flip-flop holds its state when T equals:

The JK flip-flop removes the invalid state of the:

A JK flip-flop toggles when:

Asynchronous inputs in flip-flops usually include:

The preset input forces Q to:

The clear input forces Q to:

Level-triggered devices respond during:

Edge-triggered devices respond at:

Race-around problem is associated with:

The race-around problem can be reduced by using:

A master-slave flip-flop uses:

Setup time is the minimum time data must be stable ____ the active clock edge.

Hold time is the minimum time data must remain stable ____ the active clock edge.

Clock-to-Q delay is the time from:

A transparent latch means the output follows the input when:

A synchronous sequential circuit changes state based on:

The present state and input determine the:

A state table lists:

A state diagram represents:

The output of a Moore machine depends on:

The output of a Mealy machine depends on:

A Mealy machine often reacts:

State reduction aims to:

Equivalent states are states that:

State assignment means:

Sequential logic analysis often starts with:

The characteristic equation of a T flip-flop is:

The characteristic equation of a JK flip-flop is:

A counter is a sequential circuit that:

An asynchronous counter is also called a:

A synchronous counter clocks all flip-flops:

Ripple counters are simpler but have more:

A mod-8 counter requires how many flip-flops?

A mod-16 counter requires how many flip-flops?

The modulus of a counter is the:

A binary up-counter counts:

A down-counter counts:

An up/down counter can count:

A decade counter is a:

A truncated counter is one that:

Counter decoding is used to:

A ring counter is made from a shift register with:

A Johnson counter is also called a:

An n-bit ring counter has how many valid states?

An n-bit Johnson counter has how many valid states?

A shift register is used to:

A SISO register stands for:

A SIPO register stands for:

A PISO register stands for:

A PIPO register stands for:

Shifting left by one bit in unsigned binary is equivalent to:

Shifting right by one bit in unsigned binary is equivalent to:

A universal shift register can:

The serial output of a shift register is usually taken from:

A bidirectional shift register can shift:

Parallel load means:

A ring counter typically starts with:

A Johnson counter sequence length of a 4-bit design is:

In a ripple counter, the clock of each stage is driven by:

Synchronous counters are generally preferred for high speed because they:

The terminal count output usually indicates:

A load input on a counter is used to:

A ring counter is less hardware-efficient than a binary counter because it uses:

Frequency division can be achieved using:

A divide-by-2 circuit can be realized using a toggle flip-flop driven by:

RAM stands for:

ROM stands for:

SRAM stores data using:

DRAM stores data using:

DRAM needs periodic:

SRAM is generally ____ than DRAM.

ROM is mainly used for:

PROM can be programmed:

EPROM can be erased using:

EEPROM can be erased:

Flash memory is a type of:

A memory cell stores:

The number of address lines needed for 1024 locations is:

The number of data lines determines the memory:

MAR in a computer system typically stands for:

MDR or MBR is used to hold:

An address decoder in memory selects:

Read operation means:

Write operation means:

Volatile memory loses data when:

Non-volatile memory retains data when:

Cache memory is typically implemented with:

Main memory is commonly implemented with:

A register is a group of:

The finite state machine model is used to design:

A state variable represents:

Unused states in sequential design should generally be:

A state assignment with fewer bit changes may reduce:

A one-hot state assignment uses:

Binary state assignment tries to use:

The excitation table of a flip-flop tells the inputs needed for:

For a D flip-flop, the required excitation to get next state 1 is:

For a T flip-flop, if present state equals next state, T should be:

For a T flip-flop, if present state must change, T should be:

FSM outputs can be represented conveniently in a:

Synchronous memory interfaces often use control lines such as:

Memory expansion can be done by increasing:

CPLD stands for:

FPGA stands for:

A PLD is mainly used to:

Compared with discrete gates, PLDs usually offer:

An FPGA is built from configurable logic blocks and:

A CPLD usually has architecture based on:

FPGA configuration is typically stored in:

A hardware description language is used to:

Verilog HDL is commonly used for:

VHDL stands for:

A module in Verilog is similar to a:

The keyword used to declare a module in Verilog is:

In Verilog, an always block is commonly used to model:

A continuous assignment in Verilog uses the keyword:

The non-blocking assignment operator in Verilog is:

Non-blocking assignments are generally preferred in clocked always blocks to model:

A testbench is used to:

Simulation helps designers to:

Synthesis converts HDL into:

Timing simulation checks:

A LUT inside an FPGA is primarily used to implement:

An HDL description can be written at behavioral, dataflow, and:

MultiSim is commonly used for:

In laboratory work, waveform viewers help observe:

A pin constraint file in FPGA flow is used to:

A clock constraint in FPGA design is used to:

Debouncing is often needed for:

Metastability is a concern when:

A synchronizer is used to:

Finite state machines on FPGA are usually coded using:

Bitstream file in FPGA flow contains:

A schematic capture tool allows designers to:

Design hierarchy in HDL helps by:

A combinational always block in Verilog should be sensitive to:

The statement `case` in HDL is often used to model:

In FPGA labs, seven-segment displays, LEDs and switches are examples of:

The main purpose of learning HDL in Digital Logic Design is to: